China advances sub-3nm chip design without EUV tools

Chinese Academy of Sciences completed early integration of stacked nanosheet-channel gate-all-around transistors using deep ultraviolet lithography, targeting sub-3-nm semiconductor nodes without EUV

China’s Academy of Sciences has completed early-stage integration of stacked nanosheet-channel gate-all-around (GAA) CMOS transistors using deep ultraviolet (DUV) lithography technology. This approach targets sub-3-nm semiconductor processing nodes, a critical advancement for high-performance chips. The work, reported by Digitimes as originating from China’s Institute of Microelectronics (IMECAS), remains in preliminary development—no mass production has begun. Crucially, this progress occurs despite U.S. sanctions blocking ASML’s sale of extreme ultraviolet (EUV) lithography tools to Chinese clients. The research was published September 19, 2026.

The significance lies in DUV lithography’s potential to bypass EUV dependency for advanced chip manufacturing. By using existing industrial DUV tools instead of the prohibitively expensive EUV systems, China aims to reduce costs and technical barriers for sub-3-nm nodes. This represents a technical pathway to scale semiconductor production without relying on sanctioned equipment.

For abundance, this could eventually lower costs for Chinese electronics manufacturing by avoiding EUV tool costs—a key factor in making computing hardware more accessible globally. However, the current stage is lab-scale, so immediate impact on prices or availability remains minimal.

What to watch: Whether this early-stage work can scale to production without EUV tools, and how it affects global semiconductor supply chains under sanctions. Caveats: Not yet mass-produced; early-stage technical implementation; does not indicate EUV tool bypass or full production capability.

Source: SCMP Tech